Experimental measurement of the effect of copper through-silicon via diameter on stress buildup using synchrotron-based X-ray source

In this work, the effect of copper through-silicon via (TSV) interconnect diameter on stress buildup in Cu TSVs was experimentally determined using a synchrotron-based X-ray microdiffraction technique. A single chip with different Cu TSV diameters (3, 5, and 8 lm), all having the same depth and processing conditions was studied. Prior to the measurements, the chip was annealed at 420 C (30 min), leading to microstructurally stable Cu TSVs. The mean measured hydrostatic stresses were (190 ± 25) MPa (3 lm diameter), (138 ± 19) MPa (5 lm diameter), and (209 ± 26) MPa (8 lm diameter), respectively. No clear relationship between the measured stress and Cu TSV diameter was observed. This trend is attributed to the operation of stress relaxation mechanisms in the polycrystalline Cu TSVs, which includes plastic deformation, grain boundary sliding, void formation/growth, and rate-controlled dislocation motion, which are often neglected in reported finite element analysis studies. Additionally, this study highlights that the thermo-mechanical behavior of Cu TSVs is significantly influenced by their thermal history. Introduction Three-dimensional integrated circuits (3D-IC), achieved by the vertical stacking of chips with different functionalities atop each other, are being pursued for advanced microelectronic packaging technology, as it results in high performing electrical circuits. 3D-IC is achieved by the use of vertical metal interconnects called through-silicon vias (TSV), which serves as the path for the transmission of electrical signals through the different stacked chips. Due to its high electrical conductivity, copper (Cu) is the preferred material for the filling of TSVs. The use of Cu TSV interconnects that run through active Si chips, provides the shortest electrical paths between the stacked chips. Additionally, TSVs enable high density interconnects, which significantly increases the input/output (I/O) ports, leading to increased performance [1]. One of the routes to further improve the performance of 3D-IC chips is by increasing interconnect density through reduction of the diameter of the TSVs. In fact, the International Technology Roadmap for Semiconductors (ITRS) projects the shrinking of the current electroplated Cu TSV diameter of (4–10 lm), to (2–3.5 lm) by 2018 in order to track the I/O roadmap [2]. It is thus essential to determine the potential thermo-mechanical reliability consequences associated with the change in Cu TSV diameter, especially as it relates to stress buildup and deformation. Experimentally, synchrotron-based X-ray microdiffraction has been demonstrated to be the most robust method for the measurements of stresses in and around Cu TSVs [3–12]. However, with the exception of the synchrotronbased experimental studies done by [6, 12], most of the stress analysis studies related to the effect of Cu TSV diameter in the open literature, have been based on finite element analysis (FEA) [13–17]. While the experimental & Chukwudi Okoro chukwudi.okoro@nist.gov 1 Semiconductor and Dimensional Metrology Division, National Institute of Standards and Technology (NIST), Gaithersburg, MD 20899, USA 2 Material Science and Engineering Division, National Institute of Standards and Technology (NIST), Gaithersburg, MD 20899, USA 3 Advanced Photon Source, Argonne National Laboratory, Argonne, IL 60439-4800, USA 4 Theiss Research, La Jolla, CA 92037, USA 123 J Mater Sci (2015) 50:6236–6244 DOI 10.1007/s10853-015-9184-9